IBM's upcoming POWER7 processor will be impressive. It manages to bring a much larger number of cores and threads while maintaining a higher clock rate of about 4GHz than anyone else. Although, not as high as POWER6's 5GHz.

It will ship in a few different packages varying the number chips per MCM (multi-chip module): a blade version with a single chip, a dual-chip MCM for the majority of the Power Servers, and a quad-chip MCM for POWER7 IH node, which are currently intended only to be used in the Blue Waters supercomputer. It's temping to think that the quad-chip modules will make it into the high-end Power 595 but a need for liquid cooling at any reasonable clock rate will probably prevent this. This will certainly cause people to be confused about the performance stats of these processors because the number of cores and threads are not the only thing that varies with the three versions. Just to confuse things further, it looks like IBM will offer the single chip and dual-chip MCM with not only 8-core chips but 6-core and 4-core also. The dual-chip "rejects" will most likely only be used in the entry level systems.

A single chip contains a maximum 8-cores with support for 4 SMT threads for a total of 32 threads per chip. Most systems will contain dual-chip MCMs which offer 64 threads per socket. Assuming that IBM offers them in dual-socket books like the POWER6 chips, it will allow for 2048 threads in the top end Power 595 system. Quite a jump from the current max of 128. Perhaps more importantly to most, the Power 520 entry level systems will now have a maximum of 64 threads versus the current 8. That is assuming they are not too expensive to offer in a low end machine. Don't let the list price fool ya: You will most likely need to pay a lot more to turn everything on and then there is OS licensing, etc.

POWER7 is the first chip to use eDRAM (embedded DRAM), which allows for a greater cache size with less transistors and also power savings compared to SRAM (typical processor cache). It is a bit slower but it seems to be worth it, especially because it allowed them to bring the cache onto the chip, which counteracted this side-effect. POWER6 had its L3 cache in separate chips on the MCM. POWER7 will have 32MB L3 cache per chip. For most people, this will translate to 64MB L3 cache per socket, which is by far the largest cache seen so far in any server. The design also has 32KB L1 instruction cache, 32KB L1 data cache, and 256KB L2 cache per core. If IBM used SRAM for the L3 cache instead of eDRAM, 32MB would have required a 2.7 billion transistor design (assuming you could), more than doubling the actual 1.2 billion for the complete POWER7.

There are now 12 execution units per core including the following:

• 2 fixed-point units
• 2 load/store units
• 4 double-precision floating-point units
• 1 vector unit (supporting VSX)
• 1 decimal floating-point unit
• 1 branch unit
• 1 condition register unit

The pipelines have also been revamped to deal with the new execution units and increased thread count.

A feature missing from POWER6 but used in previous POWER chips, out-of-order execution, is being put back into POWER7. This is not only a performance boost but may allow some people stuck on POWER5 for software reasons to migrate to the POWER7 systems.

The Processors are directly connect as they were with POWER6. In fact, the POWER7 will actually be available as an upgrade for the Power 570 and Power 595 systems (with a few exceptions).

As for memory, POWER7 has two dual-channel DDR3 memory controllers per chip. IBM has stated that these controllers can sustain 100GB/s of bandwidth per chip. This would translate to an aggregated sustained rate of 6.4TB/s (8TB/s theoretical peak) of memory bandwidth.

These numbers aren't confirmed yet but they appear to be off the charts compared to previous generation systems from anyone. Unfortunately, it is also likely their total price tag is too.